Sequential Prefetching in Multi-Level Cache Hierarchies

cache, performance evaluations, prefetching As processor clock rates increase the memory hierarchy is hard pressed to keep up. One way of mitigating the increasing gap between processor and memory is by prefetching items from memory before they are requested by the processor. Various algorithms perform better or worse depending on how accurately they predict the needed items and in how timely a manner they move them from lower levels of the memory hierarchy into the processor. This study centers on simple sequential prefetching which will serve as a baseline for future investigations into smarter prefetch algorithms.